A semiconductor integrated circuit is designed at RTL (Register Transfer Level).
In circuit design at RTL, the operation of a combined circuit is described. A combined circuit receives, as an input, an output of a flip flop functioning as a register and performs an output according to the state of the input.
In recent years, the circuit scale of an integrated circuit is increased and circuit design using RTL takes much time.
Accordingly, a technique called high level synthesis for automatically generating RTL using a high level language, which is more abstract than RTL, has been proposed and high level synthesis tools for achieving high level synthesis are now on the market. Examples of the high level language are the C language, the C++ language, and the SystemC.
In addition, when RTL is generated by the high level synthesis, the circuit scale of a semiconductor integrated circuit may be reduced as compared with the case in which RTL is generated manually. This is because circuit sharing can be performed automatically in high level synthesis.
The high level synthesis has been used to design an ASIC (Application Specific Integrated Circuit), and has been also often applied to an FPGA (Field Programmable Gate Array).
In the case of the ASIC, as the number of memories to be used and the number of multipliers to be used are increased, the circuit scale is enlarged.
In contrast, since memories and multipliers are provided in the FPGA in advance, the circuit scale of the FPGA is not enlarged as long as the number of memories to be used and the number of multipliers to be used do not exceed the number of provided memories and the number of provided multipliers.
However, when a complicated process such as filtering is performed many times, the number of multipliers to be used exceeds the number of multipliers provided in the FPGA.
In this case, the bit width of multiplication may be reduced or algorithm may be changed so as not to use multiplication to reduce multipliers to be used. If the bit width of multiplication is reduced, the accuracy of computation becomes lower. If the algorithm is changed, the number of computations is increased.
In addition, if an FPGA including more multipliers is selected, the cost is increased.
A multiplier is an example of a computing unit including a plurality of logic devices and is configured with a plurality of logic devices provided in an FPGA.
Therefore, the design needs to be made so that the number of computing units other than multipliers does not exceed the number that can be configured using logic devices provided in an FPGA.
As described above, circuit sharing is performed automatically in high level synthesis. Accordingly, computing units are shared by high level synthesis, the number of computing units to be used is reduced, and the number of computing units to be used may fall within the range that can be mounted on an FPGA.
Patent Literature 1 discloses the generation of a circuit that shares hardware resources between parallel descriptions.
Patent Literature 2 discloses reduction in the circuit scale by detecting the sub-graph for which the circuit area reduced by execution in a common circuit is large.
However, Patent Literature 1 and Patent Literature 2 do not disclose reduction in the number of computing units to be used by increasing memories to be used. That is, Patent Literature 1 and Patent Literature 2 do not disclose reducing the number of computing units to be used by effectively utilizing unused memories in an FPGA so that the number of computing units to be used falls within the range that can be mounted on an FPGA.
Since the conventional high level synthesis tool converts arrays to registers or memories according to an instruction of the designer, the number of memories to be used is not increased to reduce the number of computing units to be used. That is, the number of memories to be used does not become the number intended by the designer or more.
When the design target is an ASIC, since the cost is increased when the number of memories is increased, the design is made so that the number of memories is reduced basically.
In contrast, when the design target is an FPGA, the effective utilization of unused memories is more efficient.
However, the effective utilization of unused memories is not performed in the conventional high level synthesis.